A 230-GHz SiGe Amplifier With 21.8-dB Gain and 3-dBm Output Power for Sub-THz Receivers

Abstract

This letter presents a 230-GHz high-gain amplifier implemented in a 0.13- μm SiGe BiCMOS technology. The amplifier consists of a single-ended cascode (CC) stage for noise optimization and two differential CC stages for power capacity consideration. A symmetrical peripheral interconnection with self-shielded bypass capacitors for gm-boosting technique realization is employed to overcome the low inherent gain. The noise components of CC transistors are investigated and a parallel-inductor-based noise reduction technique is adopted to improve the noise figure (NF). The proposed amplifier provides a measured gain of 21.8-dB at 232 GHz with a 3-dB bandwidth of 35 GHz and a simulated NF of 10.5 dB at 230 GHz. The measured output power and maximum power-added efficiency (PAE) at 225 GHz is 3.5 dBm and 2.9%, respectively. The amplifier occupies a small area of 0.154 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a moderate power of 66 mW. Remarkable performances including gain, NF, bandwidth, and output power enable the amplifier to be adopted as either a low noise amplifier (LNA) or a driver amplifier in the sub-terahertz (sub-THz) receivers.