A 22ns 4K-bit SRAM fabricated with direct electron beam lithography

Abstract

A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , and Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.