A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor

Geunsook Park,Jingming Yao,Vincent C Venezia,Zhiqiang Lin,Tiejun Dai,Lindsay A Grant,Keiji Mabuchi,Alan Chih-Wei Hsuing,Yu-Shen Yang,Tongtong Yu

doi:10.1109/iedm19573.2019.8993606

A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor

Geunsook Park, Jingming Yao + Show 8 more

https://doi.org/10.1109/iedm19573.2019.8993606

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Publication Date: Dec 1, 2019

Citations: 11

Affiliation: Vision Technology (United States)

#Global Shutter CMOS Image Sensor #Parasitic Light Sensitivity + Show 8 more

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Abstract

This paper presents a 2.2μm pixel pitch back side illuminated (BSI) Voltage Domain Global Shutter (VDGS) image sensor with Stacked Pixel Level Connection (SPLC) and full backside Deep Trench Isolation (DTI). With these cutting edge technologies, Full Well Capacity (FWC) more than 12,000 electrons and parasitic light sensitivity (PLS) larger than 100 dB are reached. A 38% Quantum Efficiency (QE) and 60% of Modulation Transfer Function (MTF) at 940nm, half Nyquist frequency (Ny/2) is demonstrated.

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