A 21-dBm $I/Q$ Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology

Abstract

This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 25 dBm and a peak output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) of 21 dBm at 1-GHz carrier frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sys</sub> ), respectively. In addition, it achieves 11.5% η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sys</sub> with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> , and at 1-GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm).