Abstract
This paper presents a Class-C VCO with noise sensitivity mitigation technique. Class-C VCO has a large parasitic capacitances between gate and source nodes and this capacitance variation causes a large frequency sensitivity to noise voltage. As a consequence, the noise from gate node become the largest noise contributor. Proposed technique can control this sensitivity by tuning the tail impedance. A 65nm CMOS prototype of the VCO demonstrates oscillation frequency from 19.35 to 22.36 GHz, the phase noise of -105.8 dBc/Hz at 1MHz offset with power dissipation of 8.7mW and Figure-of-Merit of -182.4 dBc/Hz.
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