A 20 Gb/s/pin 1.18pJ/b 1149µm2Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS

Abstract

This paper presents an inverter-based 4-tap addition-only feed forward equalization (FFE) transmitter (TX) for compact and power-efficient single-ended memory interfaces. Area and power efficiencies of I/Os are increasingly important as I/Os are becoming faster, more complex, and larger; whereas, the area and power budget is limited. Source-series termination (SST) drivers, which are widely used in FFE TXs, provide good linearity and good impedance matching; however, the linear resistors occupy too much area and add significant parasitic capacitance, thereby dissipating additional power [1] (Fig. 28.4.1). On the other hand, inverters occupy a small area and are power-efficient, but matching their impedance and controlling their output voltage is difficult due to their nonlinear behavior. For example, replacing SST drivers in a conventional FFE (C-FFE) with inverters results in the pull-up PMOSs and pull-down NMOSs to turn on simultaneously during FFE tap subtraction. In this case, the output voltage is not well defined, since it is sensitive to supply noise, mismatch, and process variation. To overcome these issues, a 4-tap addition-only FFE (A-FFE) is proposed: it improves area, power consumption, and the resulting voltage swing, as well as its robustness to coefficient errors (Fig. 28.4.1).