A 2-V 7.2° jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control

Abstract

This paper proposes an AM-suppression CMOS amplifier that incorporates a discrete-level automatic gain control (AGC) with a hysteresis hard limiter in order to reduce magnitude dependent jitter and speed up AM-suppression response. The gain control that is composed of a transition-based magnitude controller and a discrete-level current-mode variable gain amplifier (VGA) does not require coherent detection and external components. The prototype amplifier demonstrates a jitter of 7.2/spl deg/ from 1-Mb/s pulse-point modulated (PPM) data input with 20-dB dynamic range (40-400 mV/sub pp/), which is six times improvement over the conventional limiter alone approach. The amplifier with an active area of 0.64 mm/sup 2/ is implemented in 0.8-/spl mu/m single-poly double-metal digital CMOS technology. It consumes 18 mW from a single 2-V supply.