A 2.7GHz sub-sampling phase-locked loop circuit

Abstract

A 2.7GHz low phase noise sub-sampling phase locked loop is introduced. The low noise performance is realized by using the sampling loop and the frequency lock loop. In the locked state, only the sampling loop works, while the frequency lock loop does not work, and the frequency divider does not work. Therefore, in-band noise generated by the phase detector and charge pump will not be amplified N2, so the sampling loop’s in-band noise will be greatly reduced. In order to reduce out-of-band noise, the voltage controlled oscillator is a LCVCO with nmos-pmos complementary structure. The PLL is based on TSMC 130 nm CMOS process. Under the working voltage of 1.8V, PLL consumes 24.6mw.