A 2.4 /5.2-GHz Dual Band CMOS VCO using Balanced Frequency Doubler with Gate Bias Matching Network

Abstract

This paper presents the design and measurement of a 2.4/5.2-㎓ dual band VCO with a balanced frequency doubler in 0.18 ㎛ CMOS process. The topology of a 2.4 ㎓ VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 ㎓ VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 ㎓ and 5.2 ㎓ VCOs are -12 ㏈m and -13 ㏈m, respectively, the doubled VCO has fundamental harmonic suppression of -25 ㏈. The measured phase noises at 5 ㎒ frequency offset are -123 ㏈c /㎐ from 2.6 ㎓ and -118 ㏈c /㎐ from 5.1 ㎓. The total size of the dual band VCO is 1.0 ㎜×0.9 ㎜ including pads.