Abstract
The low-voltage power capabilities of a low-cost high-performance silicon bipolar process were investigated. By optimizing the emitter finger layout, epilayer thickness, and collector doping level, efficiency values up to 83% were achieved by on-wafer load-pull measurements on a single-cell test device operating at 1.8 GHz and 2.7-V power supply. The detrimental effect of the emitter distributed resistance on the current capability of long-emitter bipolar transistors was also considered.. An analytical model for a proper device design was derived and experimentally validated. Using the optimized unit power device, a 1.8-GHz 2.7-V three-stage monolithic power amplifier was implemented, which provides a 57% power-added efficiency and a 33-dB gain while delivering a 34-dBm output power to the load.
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