A 180 nm low power CMOS operational amplifier

Abstract

This paper presents the design of two-stage operational amplifier (Op Amp). The circuit was designed in standard 180 nm digital n-well CMOS process. The design consists of very less number of transistors, hence the design is area optimized. Achieved open loop gain of the amplifier is 74.89 dB. The unity gain bandwidth (UGB) is 7.3 MHz and the phase margin is 48 degree with a 10 pF capacitive and 1 M ohm resistive load. The average power consumption of the amplifier is 0.402 mW and slew rate is 10 V/us.