A 16.6 cm/sup 2/ large area integrated circuit consisting of 9 video signal processors

Abstract

In this paper we introduce a large area integrated circuit (LAIC) called MAXPE9 which integrates 9 programmable video signal processing elements (PEs) on an area of 16.6 cm/sup 2/. Each PE has a peak arithmetic performance of 1 giga operations per second (GOPS). Due to yield considerations redundancy concepts have been implemented that even in the presence of production defects result in working chips utilizing a lower number of PEs. Each PE has built in self-test (BIST) capabilities which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PEs are switched off. Only the PEs passing the BIST are used for video processing tasks. Furthermore, the global input and output buses can be reconfigured using arrays of laser fuses and laser links, thus circumventing defects which are otherwise lethal for the complete chip. Prototypes have been fabricated in a 0.8 /spl mu/m CMOS process structured by masks using wafer stepping with overlapping exposures. Employing the redundancy, on these prototypes up to 6 PEs per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS per chip for video coding tasks (like H.261, MPEG-1 and MPEG-2).