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Abstract
A high speed, low power 16:1 serializer has been developed with a commercial 0.25 μm silicon-on-sapphire CMOS technology. The serializer operates from 4.0 to 5.7 Gbps. The total jitter is 62 ps and the eye opening of the bathtub curve is 122 ps at bit error rate of 10−12 at 5 Gbps. Power consumption is 463 mW at 5 Gbps. A proton beam test indicates the serializer is suitable for applications in high energy physics experiments.
Highlights
A high speed, low power 16:1 serializer has been developed with a commercial 0.25 μm silicon-on-sapphire CMOS technology
The serializer consists of a serializing unit, a phase lock loop (PLL) clock generator and a CML driver as shown in figure 1
Two complimentary 2.5 GHz clock signals are required to speed up the D-flip-flop in the last 2:1 multiplexer
Summary
The serializer consists of a serializing unit, a phase lock loop (PLL) clock generator and a CML driver as shown in figure 1. The last 2:1 multiplexer needs to be optimized to work at the highest speed or 2.5 GHz. Two complimentary 2.5 GHz clock signals are required to speed up the D-flip-flop in the last 2:1 multiplexer. With a 312.5 MHz reference clock input, the PLL clock generator provides 2.5 GHz, 1.25 GHz, 625 MHz, and 312.5 MHz clock signals to the serializing unit. The PLL can be configured to lock to either the rising or falling edge of the reference clock. This edge-selection feature is useful for the users to latch data with optimal timing. All the I/O pins have electrostatic discharge (ESD) protection except the high speed serial data output pins
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