Intelligent systems for particle detectors in environmental applications and High-Energy Physics

Abstract

Over the last decades, improvements in microelectronics technology have fostered signicant progress in all fields of engineering, science and also in radiation detection. The main challenge in designing radiation detectors is to develop systems based on front-end electronics that is able to cope with high radioactive environment, satisfy very high resolution requirements and comply with high particle rates. This thesis work focuses on the analysis and development of novel and intelligent solutions for electronics system, especially suited for radiation detectors. In particular, two different applications are considered here. The first one concerns the design of a portable and affordable detector system for continuous indoor Radon detection, based on SiPM technology. A simple analog front-end with optimized low-noise performances and reduced power consumption has been designed for counting each alpha particle that occurs in the detector after Radon decay. The readout electronics is integrated with a suite of environmental sensors on a full-custom Printed Circuit Board. Compared to all the commercial Radon detector nowadays available, the developed system is able to detect reliable value of indoor Radon concentration within few hours. The system also exploits the recent capabilities of microelectronic devices by including advanced functions such as Bluetooth data transmission and energy harvesting. In high-energy physics experiments, with particular emphasis on the HL-LHC environment, pixel detectors have to satisfy aggressive requirements concerning high granularity, high rate capability and low power consumption. With the advent of accessible modern technology such as 65 nm CMOS, the processing speed and reduced power consumption can be achieved. In order to meet such specications, a new pixel mixed signal ASIC has been designed as a prototype front-end for the HL-HLC pixel readout system, within the framework of RD53 collaboration. The ASIC front-end includes signal processing and synchronous analog-to-digital conversion within one Bunch Crossing period. Thus, the emphasis of the work is on the feasibility of a synchronous ADC within the HL-LHC environment, able to ensure high performances in terms of low noise, power dissipation and high speed. Finally, a novel and intelligent digital architecture has been proposed, in order to focus the eorts of the front-end on the implementations of three main features: a novel data sparsication method, a clusterization scheme at the hardware level itself and fast Region-Of-Interest (ROI) trigger capability.