Abstract
A 320MS/s 14bit pipelined SAR ADC in 40nm CMOS technology is presented in this paper. Considering the non-ideal factor of key nodes caused by many modules connected to them, and mismatch between inter-stage residue amplifier and comparator in SAR ADC, both of them have bad effect on the performance of the pipelined SAR ADC. To solve these problems, this design uses dynamic amplifier alternately functioned as the pre-amplifier in the comparator for background gain calibration, the pre-amplifier in the comparator for SAR ADC conversion and the inter-stage residue amplifier. The multiplexing of dynamic amplifier relieve the interference of key nodes and the parasitic capacitance of capacitor array top plate. And a background gain calibration scheme is proposed for the dynamic amplifier.
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