Abstract
This paper presents a 14-bit 2.5 GS/s current-steering digital-to-analog converter (DAC) in 65 nm CMOS. Small transistors are utilized in this design to reduce the 3rd-order harmonic distortion caused by finite output impedance. However, the adoption of small transistors increases the 2nd-order harmonic distortion and degrades the spurious-free dynamic range (SFDR). Hence a digital pre-distortion (DPD) scheme is proposed for 2nd-order harmonic distortion cancellation. In addition, techniques including dynamic element matching (DEM), double-data-rate (DDR) quad switch and always-on cascode switch are employed in this design to further enhance the SFDR. Simulation results show > 70 dB SFDR for input frequencies from 34 MHz to 1.2 GHz. The DAC consumes 375 mW from a dual 1.2/2.5 V power supply.
Published Version
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