Abstract
This article presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatches arise from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35-?m BiCMOS (SiGe) takes an area of 10.2 mm2, reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5-MHz input and draws 1.4 W from a 3.0-V supply.
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