A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

Abstract

This paper presents the implementation of a low-jitter system clock generator for low-band ultra-wideband (UWB) application based on a wide-range adaptive-bandwidth delay-locked loop (DLL). The false-locking problem commonly along with the wide-range DLL is eliminated by the proposed digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristic over a wide frequency range and across process, voltage, and temperature (PVT) variations. Fabricated in a 0.18 /spl mu/m CMOS technology, the design achieves an output multiphase sampling clock rate of 1 to 4 GHz and exhibits the maximum input tracking jitter of 12.06 ps (rms) and 88.9 ps (pk-pk) over the operating frequency range from 31.25 to 125 MHz. The prototype occupies an active area of 360 /spl times/ 245 /spl mu/m/sup 2/ and consumes 32 mW from a 1.8-V supply at 125 MHz.