A 130-nm RHBD SRAM With High Speed SET and Area Efficient TID Mitigation

Abstract

A radiation hardened by design 5 kB static random access memory appropriate for embedded system on a chip integrated circuits is presented. High speed dual redundant control logic suppresses single event transients, allowing 500 MHz operation. Dynamic supply modulation, reverse body bias, and array supply collapse are investigated, in place of annular layout, to suppress leakage current increases due to total ionizing dose effects. These approaches allow the use of two-edge NMOS transistor layout resulting in increased packing density. The design has been fabricated using a 130-nm bulk CMOS process; the parts were then tested and found to be functional. Experimental results from TID testing using a Co-60 gamma radiation source as well as heavy ion testing results are presented.