SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation

Abstract

Share of leakage in total power consumption of static RAM (SRAM) memories is increasing with technology scaling. Reverse body biasing increases threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), which exponentially reduces subthreshold leakage, but it increases SRAM access delay. Traditionally, when all cells of an SRAM block used to have almost the same delay, within-die variations are increasingly widening the delay distribution of cells even within a single SRAM block, and hence, most of these cells are substantially faster than the delay set for the entire block. Consequently, after the reverse body biasing and the resulting delay rise, only a small number of cells violate the original delay of the SRAM block; we propose to replace them with sufficient number of spare rows/columns of SRAM. Our experiments show that the leakage can be reduced by up to 40% in a 90-nm predictive technology by adding less than ten spare columns to an 8-kB SRAM array for a negligible penalty in delay, dynamic power, and area in the presence of 3% uncorrelated random delay variation.