Abstract
A 12-Channal 120-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier(TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is stimulation using a 0.18μm CMOS process. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. An isolation structure combined with P+ guard-ring (PGR), N+ guard-ring (NGR), and deep-n-well (DNW) for parallel amplifiers is employed to reduce the crosstalk and suppress the substrate noise coupling effectively. The tiny photo current received by the receiver AFE is amplified to voltage swing of 400. The results indicate that, with a photodiode parasitic capacitance of 500fF. Post-layout simulations demonstrate that a single channel optical receiver front-end amplifier achieves conversion gain of 91.6 dB and −3 dB bandwidth of 8.7 GHz. Operating under a 1.8V supply, circuit power dissipation is 1140 mW and its sensitivity isl8.5μA for BER of 10–12 and the chip size is733 μm × 3226μm.
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