A 12bit 39ps two-step Time-to-Digital Converter in 40nm CMOS

Abstract

This paper presents a two-step time-to-digital converter(TDC). Using a proposed self-biased phase-locked loop (PLL) based 64-phase multiphase clock generator as clock source of the phase interpolator, this TDC achieves a fine resolution of 39 ps and is not sensitive to process, voltage and temperature (PVT) variations. A dual-edge counter synchronization circuit is adopted to avoid the synchronization error between the coarse and fine stage of the TDC with low power and a small area. Designed in 40-nm CMOS, the proposed TDC achieves 39-ps resolution, 12-bit dynamic range with 1.1-ns conversion time, 0.2-mW power consumption, a core active area of 0.021 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , as shown by the post-layout simulation results.