A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique

Abstract

This paper presents a prototype of 12-bit, 3.3MS/s non-binary pipeline cyclic analog-to-digital converter (ADC) with correlated level shifting (CLS) technique and an on-chip non-binary to binary logic block. The proposed ADC is designed in 4-stage pipeline structure, and each pipeline stage is a non-binary cyclic ADC based on s-expansion, which tolerates the non-idealities of capacitor mismatch and finite amplifier gain. We also provide the CLS technique for cyclic ADC stage to obtain high SNR with small capacitors in low supply voltage. Furthermore, this ADC includes an on-chip non-binary to binary conversion logic block. The radix-value self-estimation and non-binary to binary encode functions are realized by simple digital circuits. A proof-of-concept ADC is designed and fabricated in 90nm CMOS technology. Measured ENOB = 10.45bit is achieved while a 208kHz sinusoid input is sampled at 3.3MS/s. The dynamic input range of ADC is extended to 1.8V while the supply voltage of 1.2V.