A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture

Abstract

This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current-steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined by a slew-rate-enhanced class AB output amplifier for high speed. Compared to resistor string DACs, current steering DACs, or resistor-capacitor hybrid DACs, the proposed DAC shows a better tradeoff between power and speed at low power application demanding a sampling clock between 1 MHz and 100 MHz. The prototype is a 12-bit DAC implemented in 0.18-μm CMOS technology with the worst measured DNL/INL of 6.38 LSB / 7.55 LSB. The analogue part power consumption is 1.24 mW and the digital part 0.5mW at 1.35-V power supply at 20-MS/s sampling rate. Its output is single-end buffered voltage with a range of 500 mV. The core area is 0.16 mm2.