A 12b 8GS/s Time-Interleaved 2b/cycle Pipelined-SAR ADC with Layout-Customized Bootstrap and Super- Source-Follower Based Open-Loop Residue Amplifier

Abstract

Direct RF sampling systems require the ADC conversion rates at multiple GS/s. Previous works [1]–[3] interleave pipeline ADCs or SAR ADCs to push the conversion rate to $\ge 8$ GS/s. However, the interleaved pipeline ADCs are generally less efficient in power. With the relatively slow SAR ADCs, the interleaved SAR ADCs demand a large number of channels, degrading the performance at high frequency. This work describes a 12b 8GS/s time-interleaved ADC which utilizes a 2b/cycle pipelined-SAR ADC in each channel to enhance the conversion rate with low power. To sample the input signal within 125ps, a layout-customized bootstrap is proposed to accelerate the start-up time. A high-linearity super-source-follower (SSF) based open-loop residue amplifier (RA) with large input/output swings and strong output power is exploited to accommodate the large residue and 500fF load, which provides $10 \times$ gain within 150ps. With Nyquist input, this 8GS/s ADC achieves a SNDR of 53.8dB and a SFDR of 67dB with a power dissipation of 1W.