A 128-channel time-to-digital converter based on the 24-phase shift-clock sampling method for RPC

Abstract

The Resistive Plate Chamber (RPC) are widely used in high energy physics (HEP) experiments. In recent years, new designs and application scenarios of RPCs abound, and an advanced time-to-digital converter (TDC) system is in demand. The TDC implemented in the field-programmable gate array (FPGA) is widely used in HEP experiments with changeable conditions as a flexible time measurement method. This article presents a multi-phase shift-clock sampling FPGA-based TDC with 128 channels. The TDC module is implemented in a Xilinx Kintex-7 FPGA. The sampling clock period (2.22 ns) is subdivided into 24 phases to achieve finer time resolution. The TDC performance measurements show that the root-mean-square (RMS) time resolution of the TDC module in the time interval measurement is 45.3 ∼ 57.7 ps, and the integral nonlinearity (INL) is smaller than 0.2368 least significant bit (LSB). In addition, some target designs are made to adapt to the application scenarios. This article also shows measurement results acquired from an RPC by this TDC. This TDC was used to measure the RPC efficiency plateau and the TOT of the RPC readout signal.