Abstract
We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply.
Highlights
In complementary metal-oxide semiconductor (CMOS) image sensor (CIS) systems, as the pixel resolution and the frame rate increases, the data transmission bandwidth between the sensor and image signal processor (ISP) continuously increases.As the speed of the interface increases, the increase in power consumption can not be avoided and this limits the available lifetime of the devices for battery-powered applications
The parallelized 40-bit data are used for clock and data recovery in a bang-bang phase detector (BBPD) and the oversampling phase detector (OSPD) of the CDR
The proposed transceiver circuits are implemented in a 65-nm low-power CMOS process with a 1.2-V supply
Summary
In CMOS image sensor (CIS) systems, as the pixel resolution and the frame rate increases, the data transmission bandwidth between the sensor and image signal processor (ISP) continuously increases. The power efficiency is one of the most important indicators for evaluating the CIS interface circuits on the sensor side. Several standardized interfaces such as D-PHY and C-PHY from the mobile industry processor interface (MIPI) alliance can support required data rates for a CIS system. Since the D-PHY requires additional lanes for clock forwarding, the effective data rate per channel must be reduced. We propose a power-efficient dual-channel CIS interface architecture using the transition characteristics inherent to image signals.
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