A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Junjie Wu,Jianhui Wu

doi:10.3390/electronics9030507

Abstract

A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

Highlights

Successive-approximation-register (SAR) ADC is quite powerful and area-efficient due to its mostly digitized structure [1,2], which is scalable with respect to process development
In [17], the gain of the dynamic amplifier was determined by capacitor ratios, which were stable under various PVT conditions but at the cost of a large analog overhead
VFS1 and VFS2 are the signal ranges of the two SAR ADCs, respectively

Summary

Introduction

Successive-approximation-register (SAR) ADC is quite powerful and area-efficient due to its mostly digitized structure [1,2], which is scalable with respect to process development. ADC usually employs merely one amplifier, since each SAR ADC can resolve more bits than in a conventional pipelined structure with flash sub-ADC. A dynamic residue amplifier (DRA) is usually employed due to its simple structure and zero static power [15,16,17,18]. In a pipelined-SAR ADC, the residue voltage of the first stage (which is the input of the dynamic amplifier) is usually smaller than the pipelined counterpart. In [17], the gain of the dynamic amplifier was determined by capacitor ratios, which were stable under various PVT conditions but at the cost of a large analog overhead. On theOn other hand,hand, this calibration scheme works in the background, so as and obtain the proper the other this calibration scheme works in the background, so to track

Architecture theProposed

Background

Operation

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Results

Conclusions