A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter

Abstract

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75- mu m CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm/sup 2/, including all digital logic and output buffers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>