A 112Gb/s Low-Noise PAM-4 Linear Optical Receiver in 28nm CMOS

Abstract

A 112Gb/s PAM-4 linear optical receiver with low noise, high linearity in 28nm CMOS is presented. The receiver signal chain consists of a transimpedance amplifier (TIA), a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. PMOS CML logic is used based on the device characteristics. The low-noise topology and novel gain control techniques together enable state-of-the-art performance. The receiver achieves 2.72$\mu$ Arms input-referred noise current, 71dB $\Omega$ transimpedance gain and 37 GHz bandwidth. It is able to provide 18.5dB dynamic range to support maximum input overload current of 1.8mApp. The total harmonica distortion (THD) is below 5% under 660mVpp output swing. This receiver consumes 96.8mW from 1.5V supply.