A 11.42-ENOB 6.02 fJ/conversion-step SAR-assisted digital-slope ADC with a reset-in-time VCO-based comparator for power reduction

Abstract

A successive approximation register (SAR)-assisted digital-slope analog-to-digital converter (ADC) with an “8-bit + 4-bit” hybrid topology is presented. In the coarse quantization with an 8-bit SAR ADC, a voltage-controlled oscillator (VCO)-based comparator with a reset-in-time function is proposed for energy saving. Once the phase detector generates the comparison result, the VCO resets to significantly reduce the power of the comparator. Moreover, in a 4-bit fine digital-slope ADC, the delay cell is reused from the VCO-based comparator to the delay line; thus, the area of the entire ADC is reduced to a certain extent. The proposed ADC is designed using 0.18-µm CMOS technology and can operate at a supply voltage as low as 0.6 V. The ADC achieves a signal-to-noise-and-distortion ratio of 70.53 dB with a sampling rate of 20 kS/s and an input frequency of 9.74 kHz. The power consumption is only 330 nW, and the Walden figure-of-merit is 6.02 fJ/conversion-step, making it suitable for low-supply low power internet-of-things applications.