Abstract
Digital-to-Analog Converter (DAC) is an important element in many digital systems that demand high-performance data conversions. Due to factors like shrinking supply voltage and budget constraints, DAC highly relied on matched components to perform data conversion. In reality, matched components are nearly impossible to fabricate, because mismatch errors always occurred between designed and actual component value. Therefore, in this work, the Dynamic Element Matching (DEM) algorithm is used, known as Partial Binary Tree Network (PBTN). PBTN reduces the complexity of the circuit and produces an output signal with fewer glitches. In this work, the op-amp built by transistors is used as an output current magnifier. Results show the simulation of 10-bit 1-MSB PBTN DAC using a non-ideal op-amp produced a DNL of -0.182979 LSB, INL of -0.959287 LSB, and power consumption of 1.108 mW.
Published Version
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