Abstract
This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, the CCRO phase progression is encoded with a bubble error suppression logic, thereby building resilience to delay mismatches from circuit/layout imperfections. The prototype circuit implemented in a 28 nm CMOS process demonstrates a combination of high resolution and high sample rate over wide range of sample rates. The TDC achieves its peak figure-of-merit (FoM) of 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear resolution and 15.4 ps time resolution, operating from a 0.55 V supply. The TDC demonstrates the highest reported linear resolution of 9.29 bits among converters operating above 100 MS/s, at 125 MS/s and 0.9 V supply, while achieving 4.4 ps time resolution and 0.16 pJ/conv.-step FoM. Further, the real-time quantizing architecture allows fast operation up to 750 MS/s, where the TDC delivers 6-bit linear resolution and 0.48 pJ/conv.-step FoM operating from 0.9 V supply.
Highlights
Integrated time-to-digital converter (TDC) circuits that measure time intervals with high precision, accuracy, and speed, have a wide range of applications
The design of conventional analog-to-digital converter (ADC) architectures with voltage/current-domain signal representation becomes increasingly difficult as semiconductor technology scales down deep into the nanometer regime, due to the diminishing voltage headroom and the decreasing intrinsic gain of the devices
We propose a TDC circuit with real-time quantization and a cyclic-coupled ring oscillator (CCRO) quantizer
Summary
Integrated time-to-digital converter (TDC) circuits that measure time intervals with high precision, accuracy, and speed, have a wide range of applications. An application that has recently gathered interest is time-domain analog-to-digital conversion [5], where time is utilized as a medium for signal representation. O. Järvinen et al.: 100-750 MS/s 11-Bit TDC With CCRO time reference for quantization, enabling high converter resolution for given conversion time. The measurement results of a prototype 11-bit TDC design in a 28 nm CMOS process demonstrate a versatile highly scalable operation over a wide range of sample rates from 100 MS/s to 750 MS/s, and delivers the state-of-the-art peak linear resolution of 9.29 bits at 125 MS/s sample rate with 4.4 ps time resolution.
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