Abstract
This paper describes a 1.0 Gbps clock and data recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380-720 MHz. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m CMOS HSPICE simulation.
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