A 10-bit 10-MS/s Asynchronous SAR ADC with Input Offset Calibration using Capacitor DAC

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) with input offset calibration is proposed to reduce input offset mismatches between multiple ADCs. The proposed input offset calibration is performed by controlling the capacitors used for scaling the input range of the SAR ADC in the capacitor digital-to-analog converter (CDAC) without the addition and modification of analog circuits. To verify the proposed input offset calibration, a 10-bit 10-MS/s SAR ADC with asynchronous architecture is implemented by using a 180-nm CMOS process with a supply voltage of 1.8 V. The power consumption and active area of the implemented SAR ADC are 2.29 mW and 0.207 ㎟, respectively. The control logic circuits added for the proposed input offset calibration occupy an area of 0.032 ㎟. The proposed input offset calibration of the SAR ADC reduces the input offset of ten LSBs to less than that of three LSBs. The measured DNL and INL are +0.60/−0.94 LSBs and +0.89/−0.93 LSBs, respectively. The ENOB is measured to 9.29 bits for the analog input signal with Nyquist frequency.