A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

Abstract

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-/spl mu/m CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V/sub pp/ differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz/spl plusmn/250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V/sub pp/ and up to 70 MHz with 0.7 V/sub pp/. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply.