A 1 V, 1.9 GHz, low distortion dual-gate CMOS on SOI mixer

Abstract

The front-end of a typical wireless receiver operating in the 1-2 GHz range uses silicon bipolar or GaAs processes. Although these processes provide good performance, they result in large area circuits, dissipate high power and are not amenable to implementation on the same chip as the remaining CMOS digital baseband circuitry. To overcome these disadvantages, RF front-ends must be implemented in CMOS technology to achieve low cost, small area and minimum power dissipation. CMOS on SOI is particularly suitable for the cointegration of RF and digital CMOS circuits because of low substrate parasitics and minimum coupling which result in high performance active and passive (inductors, capacitors) elements, making it an ideal technology for RF front-ends and specifically mixer implementations. This paper presents a 1 V, 0.5 /spl mu/m CMOS on SOI dual-gate mixer with a RF input of 1.93 GHz and an IF output of 210 MHz. Compared to recently reported mixers (Sullivan et al., 1999), this design has higher conversion gain, lower NF, 50 /spl Omega/ on-chip RF matching, excellent IIP3 and low power dissipation.