Abstract
This paper describes a fully differential 1-tap decision feedback equalizer in 0.18-mum SiGe BiCMOS technology. The circuit is capable of equalizing NRZ data up to 40 Gb/s. A look-ahead architecture is employed with modifications to reduce complexity in the high-speed clock distribution. An analog differential voltage controls the tap weights. The design is fabricated in 0.18-mum SiGe BiCMOS technology with a 160-GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> . It occupies an area of 1.5 mmtimes1 mm and operates from a 3.3-V supply with 230-mA current. It is the first feedback equalizer at 40 Gb/s
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