A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control

Abstract

This article presents a support vector machine (SVM) processor that supports both seizure detection and on-chip model adaptation for epileptic seizure control. Alternating direction method of multipliers (ADMM) is utilized for highly parallel computing for SVM training. From the algorithm aspect, minimum redundancy maximum relevance (mRMR) and low-rank approximation are exploited to reduce overall computational complexity by 99.4% while also reducing memory storage by 90.4%. For hardware optimization, overall hardware complexity is reduced by 87% through a hardware-shared configurable coordinate rotation digital computer (CORDIC)-based processing element array. Parallel rotations and folded structure for the approximate Jacobi method reduce overall training latency by 98.6%. The chip achieves a detection performance with a 96.6% accuracy and a 0.28/h false alarm rate within 0.71 s with the power dissipation of 1.9 mW. The proposed SVM processor achieves the shortest detection latency compared with the state-of-the-art seizure detectors. It also supports real-time model adaptation with a latency of 0.78 s. Compared with previous designs, this work achieves a $22\times $ higher throughput and a $162\times $ higher energy efficiency for SVM training.