A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS

Abstract

A 0.5-4GHz fractional-N phase locked loop (PLL) capable of spread-spectrum clock (SSC) generation in low leakage 28nm CMOS process is presented. A novel technique of bandwidth control enables the PLL to be used for clocking multi-protocol SERDES PHYs. The PLL has a voltage controlled ring oscillator and achieves a phase noise of-86dBc/Hz at 1MHz offset for 4GHz operation. It supports an input frequency range of 10MHz to 100MHz, occupies an area of 0.092mm2 and consumes 9.56mW power.