Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling

Abstract

Owing to verification bottleneck, analog and mixed signal IPs like Phase Locked Loop (PLL) take considerable amount of design cycle time. To evade this, we have presented detailed real value modeling approach, which facilitate analog accuracy in digital simulation, for Spread Spectrum Clock Generator (SSCG) PLL. SSCG PLLs are universally used to avoid Electro-migration Interference (EMI), major cause for silicon failure. The objective of the work is to accurately model SSCG PLL along with individual analog effects and noise behavior for full functional Mixed Signal System on Chip (MSSoC) verification. The accuracy of proposed modeling approach is validated through equivalence check with Post Layout SPICE (PLS). Such efficient models provide simulation speed-up hence, reducing Time To Market (TTM).