Abstract
In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high $\vert \text{V}_{\mathrm {GS}}\vert $ for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the $\vert \text{V}_{\mathrm {GS}}\vert $ decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as -9 % supply voltage variation, or -20 °C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 °C temperature variation, the power consumption of SAR ADC decreased without performance degradation.
Highlights
The successive approximation register (SAR) analog-todigital converters (ADCs) are the most promising candidate for low power applications such as battery-powered sensor nodes and bio-medical systems
SAR ADCs operating at low supply voltage for power efficiency have been reported [1]–[9]
IMPLEMENTATION Fig. 5. shows a block diagram of the proposed SAR ADC. It consists of 8-12-bit reconfigurable split-capacitor capacitive digital-to-analog converter (C-DAC), detection-N-control (DNC), adaptively accelerating C-DAC settling switch (ACS), and adaptively boosting comparator (ABC) blocks
Summary
The successive approximation register (SAR) analog-todigital converters (ADCs) are the most promising candidate for low power applications such as battery-powered sensor nodes and bio-medical systems. Several ADCs involved temperature compensation technique for comparator under the low supply voltage, and PVT-stabilized technique for dynamic amplifiers [9]–[11] Besides these problems, conversion speed can be severely affected by PVT variations. The proposed system detects the PVT variation by monitoring the conversion speed and controls the supply voltage to reduce power consumption. At some PVT conditions such as FF corner, higher supply voltage, or 80 ◦C, the accelerated conversion speed causes large power consumption. If the EOC precedes the sampling clock because of fast conversion speed, the PVT SENSING block decreases the DDNC to decelerate the conversion speed and reduce the power consumption. Tcom should be shorter than Tdelay, i.e., detection-andcontrol has the following criteria
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