A 0.18 μm CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator

Abstract

This PLL features a hot-standby PLL (HSPLL) architecture and noise-immune circuit techniques. With this architecture, both fast lock time and low jitter are achieved by the system transfer function being changed; it is unnecessary to vary the values of system parameters in an attempt to reduce lock time. The HSPLL uses a reconfigurable delay line (RDL) that, depending upon the state of its switch circuit (SC), can operate either as a voltage-controlled delay line (VCDL) or a voltage-controlled oscillator (VCO). When the RDL is operating as a VCDL (i.e. when the total circuit is a VCDL-PLL, a first-order system), lock time is fast and jitter is low, but it is difficult to generate a frequency-multiplied signal. This makes the VCDL-PLL configuration appropriate for the unlocked state. Then, at the instant that the HSPLL changes from the unlocked state to the locked, the condition of the SC is changed to create a VCO-PLL, a second-order system in which it is easy to generate a frequency-multiplied signal but difficult to achieve fast lock time (i.e. a situation well-suited to a locked state). This HSPLL architecture allows use of the respective advantages of both VCDL- and VCO-PLLs without having to suffer from their various disadvantages. The HSPLL is implemented in 0.18 /spl mu/m CMOS and two-layer metal technology. 2010 transistors are integrated into a 480/spl times/450 /spl mu/m/sup 2/ die area. The supply voltage is 1.0 V, the power dissipation is about 2 mW, the input signal frequency is 50 MHz, and the output signal frequency is 200 MHz.