A 0.5–11 GHz CMOS Low Noise Amplifier Using Dual-Channel Shunt Technique

Abstract

A 0.5-11 GHz CMOS low noise amplifier (LNA) is proposed, with a new dual-channel shunt technique implemented, where one channel uses inductive-series peaking to provide flat gain over 0.5 to 11 GHz, and another channel adopts resistive feedback to realize wideband input impedance matching. The LNA was fabricated using the TSMC 0.18 ¿m CMOS process, achieving a maximum power gain of 10.2 dB. Its input return loss is better than 9 dB over a 3 dB bandwidth of 0.5-11 GHz at a power consumption of 14.4 mW. The measured noise figure is from 3.9 to 4.5 dB, and the IIP3 is -9.1 dBm at 6 GHz. The overall chip size is about 0.54 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .