A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis

Abstract

We propose a multimodal PAM4/nonreturn to zero (NRZ) transceiver, including an adaptive ultra-wide range receiver and power noise-stabilized transmitter. The multimodal transmitter features a PAM4 emphasis driver and stabilizer, which are applied to reduce distortion impact and power-induced jitter. Installing an aggressor circuit allowed us to analyze the influence on the input buffer of the interface block and the influence on the whole system by varying the frequency and activation rate. The multi-modal receiver features a wide-range phase detector to optimize jitter tolerance at each speed while supporting both clock-forward and clock-embedded modes. Our proposed RX supports three selectable modes, each of which has a tradeoff between jitter tolerance and power. An adaptive clock data recovery (CDR) controller selects the optimum CDR mode according to transmitter jitter performance to reduce power consumption while ensuring interoperability. We also derived CDR power and the effect of latency accompanying it from an open loop transfer function. A test chip was fabricated using a 28-nm CMOS process that achieved 0.25–27-Gb/s wide-range operation and a 33% power reduction compared to conventional architecture without the adaptive controller, resulting in 3.8-pJ/bit energy efficiency for TX and 6.2-pJ/bit for RX.