99.83% Switching energy reduction over conventional scheme for SAR ADC without reset energy

Abstract

A high-efficient switching method for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. With the proposed variable resolution SAR ADC architecture, the average switching energy and area can be reduced by 99.60 and 73.54% respectively compared to the conventional scheme. Combined with C–2C capacitor array and unilateral monotonic scheme, the proposed two-step architecture achieves 99.83% less average switching energy and 76.37% less area reduction over the conventional approach. Furthermore, these two methods have no rest energy consumption.