80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold

Abstract

An inverter-based track-and-hold circuit that merges the functions of buffering and sampling is proposed, simultaneously improving linearity, bandwidth and power efficiency when compared to state-of-the-art designs. The circuit operation and its governing equations are presented, and simulation results of an 80 GS/s, 5.5 ENOB time-interleaved prototype consuming 25 mW from a 0.7 V supply demonstrate the advantages of the proposed topology using a predictive 7 nm FinFET CMOS technology.