6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology

Abstract

FDSOI technology with ultra-thin body and box (UTBB) provides a back-gate terminal which can be effectively used to forward bias or reverse bias the MOSFET. Using the back-gate terminals, the SRAM 6T bitcell has been modified resulting in four variants which are differently capable of better read and write margins, enabling lower operating voltage. At the same time, all the variants give improvement in the cell current and write time. The four variants have been fabricated in 28nm High-K Metal-Gate FDSOI technology and benchmarked against the standard 6T bitcell. There is a gain of 67%(25%) in cell current at 0.6V(1V) and 45% reduction in write time at 0.6V. Along with this, a gain in write margin or a gain in static noise margin can be chosen from the various variants. Applicability of read stability and write assist techniques to these bitcells has also been discussed.