Abstract

This paper presents the design and performance of a 6.6kW, three-phase interleaved, high density Totem Pole (TTPL) Power Factor Correction (PFC) based on SiC MOSFETs. The converter is operated at 100 kHz and in Continuous Conduction Mode (CCM). Key design features, components selection, and control scheme are discussed in detail. The digital controller enables phase shedding and adaptive dead-time control to improve the efficiency and power factor at light load. The SiC isolated gate driver is designed to have 4 A peak and 6A sink current and contains the two-level turn-off circuit for short-circuit protection. Experimental results from the 6.6kW design show that very high peak efficiency of 98.9%, and less than 2% THD are achieved at high line (240 V) AC input with 400 V DC output.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call