Abstract
Digital video capture and playback have become standard features for many handheld consumer electronic products such as digital still cameras, camera phones, camcorders, and PDAs. Video compression is used in these products for accommodating the limited storage and transmission requirements. Video compression standards (MPEG/ITU-T) are popular as they guarantee interoperability among products. The block-based nature of these standards makes them implementation friendly to embedded video solutions on programmable multimedia chips. Because of the limited memory size and processing power of programmable multimedia chips used in consumer appliances, the embedded video codec design needs to make good tradeoff between quality and complexity. Particularly, efforts should be made to develop lightweight algorithms for motion estimation, mode decision, rate control, error detection, and error concealment. Understanding of the chip architecture and the codec algorithm is the key to designing the most efficient embedded video codec. Characteristics of the chip architecture and codec algorithm determine the code partitioning, data flow, and memory allocation of the codec. A good tradeoff between code size and code efficiency, minimization of memory access, memory bank conflicts, cache miss rate and DMA transfer overhead, and balanced processor loading in concurrent mode are some of the key factors that contribute to an efficient implementation of embedded video codec.
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